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Field Programmable Logic And Applications

13th Internatonal Conference, Fpl 2003, Lisbon, Portugal, September 1-3, 2003 : Proceedings

Field Programmable Logic And Applications - Cheung, Peter Y. K. (EDT)/ Constantinides, George A. (EDT)/ De Sousa, Jose T. (EDT) - ISBN: 9783540408222
Prijs: € 113,50
Levertijd: 4 tot 6 werkdagen
Bindwijze: Boek, Paperback (01-10-2003)
Genre: Theoretische informatica
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Beschrijving

This book contains the papers presented at the 13th International Workshop on Field Programmable Logic and Applications (FPL) held on September 1-3, 2003. The conference was hosted by the Institute for Systems and Computer Engineering-Research and Development of Lisbon (INESC-ID) and the Depa- ment of Electrical and Computer Engineering of the IST-Technical University of Lisbon, Portugal. The FPL series of conferences was founded in 1991 at Oxford University (UK), and has been held annually since: in Oxford (3 times), Vienna, Prague, Darmstadt,London,Tallinn,Glasgow,Villach,BelfastandMontpellier.Itbrings together academic researchers, industrial experts, users and newcomers in an - formal,welcomingatmospherethatencouragesproductiveexchangeofideasand knowledge between delegates. Exciting advances in ?eld programmable logic show no sign of slowing down. New grounds have been broken in architectures, design techniques, run-time - con?guration, and applications of ?eld programmable devices in several di?erent areas. Many of these innovations are reported in this volume. The size of FPL conferences has grown signi?cantly over the years. FPL in 2002 saw 214 papers submitted, representing an increase of 83% when compared to the year before. The interest and support for FPL in the programmable logic community continued this year with 216 papers submitted. The technical p- gram was assembled from 90 selected regular papers and 56 posters, resulting in this volume of proceedings. The program also included three invited plenary keynote presentations from LSI Logic, Xilinx and Cadence, and three industrial tutorials from Altera, Mentor Graphics and Dafca.

Details

Titel: Field Programmable Logic And Applications
auteur: Cheung, Peter Y. K. (EDT)/ Constantinides, George A. (EDT)/ De Sousa, Jose T. (EDT)
Mediatype: Boek
Bindwijze: Paperback
Taal: Engels
Aantal pagina's: 1155
Uitgever: Springer-Verlag New York Inc
Plaats van publicatie: DE
Publicatiedatum: 01-10-2003
NUR: Theoretische informatica
Afmetingen: 241 x 158 x 44
Gewicht: 1496 gr
ISBN/ISBN13: 3540408223
ISBN/ISBN13: 9783540408222
Intern nummer: 7255881

Inhoudsopgave

'Technologies and Trends.- Reconfigurable Circuits Using Hybrid Hall Effect Devices.- Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.- Communications Applications.- Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.- Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S.- High Level Design Tools 1.- An Algorithm Designer's Workbench for Platform FPGAs.- Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset.- Reconfigurable Architectures.- ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.- Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.- Arbitrating Instructions in an ??-Coded CCM.- Cryptographic Applications 1.- How Secure Are FPGAs in Cryptographic Applications?.- FPGA Implementations of the RC6 Block Cipher.- Very High Speed 17 Gbps SHACAL Encryption Architecture.- Place and Route Tools.- Track Placement: Orchestrating Routing Structures to Maximize Routability.- Quark Routing.- Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms.- Multi-context FPGAs.- Virtualizing Hardware with Multi-context Reconfigurable Arrays.- A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.- Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.- Cryptographic Applications 2.- Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES.- Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm.- An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers.- Low-Power Issues 1.- Data Processing System with Self-reconfigurable Architecture, for Low Cost, Low Power Applications.- Low Power Coarse-Grained Reconfigurable Instruction Set Processor.- Encoded-Low Swing Technique for Ultra Low Power Interconnect.- Run-Time Configurations.- Building Run-Time Reconfigurable Systems from Tiles.- Exploiting Redundancy to Speedup Reconfiguration of an FPGA.- Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration.- Cryptographic Applications 3.- Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA.- An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.- Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.- Compilation Tools.- Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.- Branch Optimisation Techniques for Hardware Compilation.- A Model for Hardware Realization of Kernel Loops.- Asynchronous Techniques.- Programmable Asynchronous Pipeline Arrays.- Globally Asynchronous Locally Synchronous FPGA Architectures.- Biology-Related Applications.- Case Study of a Functional Genomics Application for an FPGA-Based Coprocessor.- A Smith-Waterman Systolic Cell.- Codesign.- Software Decelerators.- A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer.- Reconfigurable Fabrics.- Extra-dimensional Island-Style FPGAs.- Using Multiplexers for Control and Data in D-Fabrix.- Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.- Image Processing Applications.- A Real-Time Visualization System for PIV.- A Real-Time Stereo Vision System with FPGA.- Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System.- SAT Techniques.- Reconfigurable Hardware SAT Solvers: A Survey of Systems.- Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.- Hardware Implementations of Real-Time Reconfigurable WSAT Variants.- Applicati

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